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Automatic Tool-Chain Testing System
Aschenbrenner, Vojtěch ; Šuška, Boris (referee) ; Hruška, Tomáš (advisor)
Project Lissom is developing environment for design application specific processors or SoC (System on Chip). Project developes tools like assembler, disassembler, simulator, C compiler etc. Environment testing is required and It's main reason for this work. The work is about software testing, types of testing and about existing testing systems. The inspiration from existing systems is used for design and implementation Lissom testing system. System is comparing tools outputs with reference files. The system needs Bugzilla client end e-mail sender for complete functionality. These tools were also created.
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Network Traffic Analysis Using NXP Processor and FPGA
Orsák, Michal ; Vrána, Roman (referee) ; Kořenek, Jan (advisor)
The primary goal of this thesis is to exploit possibilites of aa entirely new hardware based on NXP LS2088 and FPGA. The secondary goal is to create firmware for this processor working out-of-box and perform optimisations of existing software for L7 analysis. This software was deeply bound to a previous hardware platform. The network processor NXP LS2088 contains many hardware accellerators and a virtual reconfigurable network. This thesis exploits all hardware parts of on this platform. Many tweaks and optimizations were performed based on this analysis to achieve maximum efficieny of software for L7 analysis. There were many intensive optimisations like rewriting for the DPDK library and new hardware or hardware synchronization of worker threads of this application. The main result of this thesis is working platform with efficient L7 analysis software which actively uses accelerators in FPGA and NXP network processor. SDK for new platform is also prepared.
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Hardware-Software Codesign Algorithms
Vlach, Jan ; Schwarz, Josef (referee) ; Fučík, Otto (advisor)
This master's thesis deals with a parallel design of the program and a technical equipment of embedded systems. It involves both a general description of the whole process and an illustration of the design, a simulation and implementation of the FIR filter. It also includes a description of the proposed program Polis and the simulation system Ptolemy. The conclusion of the project is devoted to a generation of simulation models in VHDL language incl. a subsequent synthesis.
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Hardware-Software Codesign Algorithms
Vlach, Jan ; Schwarz, Josef (referee) ; Fučík, Otto (advisor)
This master's thesis deals with a parallel design of the program and a technical equipment of embedded systems. It involves both a general description of the whole process and an illustration of the design, a simulation and implementation of the FIR filter. It also includes a description of the proposed program Polis and the simulation system Ptolemy. The conclusion of the project is devoted to a generation of simulation models in VHDL language incl. a subsequent synthesis.
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|
|
Network Traffic Analysis Using NXP Processor and FPGA
Orsák, Michal ; Vrána, Roman (referee) ; Kořenek, Jan (advisor)
The primary goal of this thesis is to exploit possibilites of aa entirely new hardware based on NXP LS2088 and FPGA. The secondary goal is to create firmware for this processor working out-of-box and perform optimisations of existing software for L7 analysis. This software was deeply bound to a previous hardware platform. The network processor NXP LS2088 contains many hardware accellerators and a virtual reconfigurable network. This thesis exploits all hardware parts of on this platform. Many tweaks and optimizations were performed based on this analysis to achieve maximum efficieny of software for L7 analysis. There were many intensive optimisations like rewriting for the DPDK library and new hardware or hardware synchronization of worker threads of this application. The main result of this thesis is working platform with efficient L7 analysis software which actively uses accelerators in FPGA and NXP network processor. SDK for new platform is also prepared.
|
|
|
Automatic Tool-Chain Testing System
Aschenbrenner, Vojtěch ; Šuška, Boris (referee) ; Hruška, Tomáš (advisor)
Project Lissom is developing environment for design application specific processors or SoC (System on Chip). Project developes tools like assembler, disassembler, simulator, C compiler etc. Environment testing is required and It's main reason for this work. The work is about software testing, types of testing and about existing testing systems. The inspiration from existing systems is used for design and implementation Lissom testing system. System is comparing tools outputs with reference files. The system needs Bugzilla client end e-mail sender for complete functionality. These tools were also created.
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